1. Field of the Invention
The present invention relates to a method for maintaining the height of a peripheral area. More particularly, the invention relates to a method of fabricating a dynamic random access memory (DRAM).
2. Description of the Related Art
Since the trend of semiconductor fabrication process is towards a linewidth of 0.25 micrometers, or below, it is particularly important to form a DRAM capacitor with an increased storage surface. Conventionally, a hemispherical grain (HSG) layer is formed on double sidewalls of a crown-shaped bottom electrode of a capacitor in order to increase the storage area of the capacitor. In a DRAM fabrication process with a linewidth of 0.21 micrometers or 0.18 micrometers, the HSG layer is commonly used. In order to form the HSG layer, the bottom electrode must be exposed before forming the HSG layer on the bottom electrode. Therefore, it is necessary to remove the oxide layer, which covers the bottom electrode, in a cell array area to expose the bottom electrode. Unfortunately, the oxide layer in a peripheral area of the same chip is also simultaneously removed. The undesirable removal of the oxide layer causes a height difference between the cell array area and the peripheral area. This, in turn, induces difficulties in the subsequent photolithographic step, such as difficulties in controlling the depth of focus (DOF).
FIGS. 1A through 1E are schematic, cross-sectional views showing a conventional method of fabricating a capacitor.
In FIG. 1A, a substrate 100 includes a cell array area 102 and a peripheral area 104. A dielectric layer 106 and a covering layer 108 are formed in sequence over the substrate 100. A contact electrode 110 is formed through the dielectric layer 106 and the covering layer 108 in the cell array area 102. A first oxide layer 112 is formed over the substrate 100. A portion of the first oxide layer 112 is removed to form an opening 114 in the cell array area 102. The opening 114 in the first oxide layer 112 exposes the contact electrode 110.
In FIG. 1B, a conformal amorphous silicon layer 116 is formed over the substrate 100. The amorphous silicon layer 116 covers the opening 114 and the first oxide layer 112.
In FIG. 1C, a second oxide layer 118 is formed over the substrate 100 to fill the opening 114. A chemical-mechanical polishing (CMP) step is performed until the first oxide layer 112 in the peripheral area 104 is exposed. The amorphous silicon layer 116 in the peripheral area 104 is completely removed. An amorphous silicon layer 116a, which remains from the amorphous silicon layer 116, is formed in the cell array area 102.
In FIG. 1D, the second oxide layer 118 is removed to expose the double sidewalls of the amorphous silicon layer 116a, which is crown shaped. A selective HSG layer 120 is formed on the amorphous silicon layer 116a. The HSG layer 120 and the amorphous silicon layer 116a together serve as a bottom electrode. A conformal dielectric film 122 is formed on the HSG layer 120. The dielectric film 122 comprises an oxide/a nitride/an oxide (ONO) layer and a nitride/an oxide (NO) layer. The dielectric film 122 serves as a dielectric layer and a capacitor.
In FIG. 1E, a conductive layer 124 is formed over the substrate 100. The conductive layer 124 serves as a top electrode of a capacitor. Because the amorphous silicon layer 116 and the HSG layer 120 are formed in the cell array area 102, after the conductive layer 124 is formed, the surface height of the cell array area 102 is higher than that of the peripheral area 104. The different heights of the cell array area 102 and the peripheral area 104 causes difficulties in deciding the depth of focus in a photolithographic step. That is, due to the height difference between the cell array area 102 and the peripheral area 104, it is difficult to select a preferred depth of focus. Therefore, the linewidth of the fabrication process may increase, and more seriously, it may be difficult to perform a photolithographic step. Thus, it is important to maintain the height of the peripheral area 104.
In order to maintain the height of the peripheral area 104, the conventional method forms a photoresist layer (not shown) to cover the first oxide layer 112 in the peripheral area 104. The photoresist layer prevents the first oxide layer 112 in the peripheral area 104 from being removed during the removal of the first oxide layer 112 in the cell array area 102, in order to reduce the height difference between the cell array area 102 and the peripheral area 104.
However, in this conventional method, it is difficult to control precisely the formation range of the photoresist layer. For example, the photoresist layer may be undesirably formed on the amorphous silicon layer 106 in the cell array area 102. Once the photoresist layer covers the amorphous silicon layer 106 in the cell array area 102, the oxide layer 112 in the cell array area 102 cannot be completely removed. The exposed surface area of the amorphous silicon layer 116 is decreased, and correspondingly, the formation of the HSG layer 120 is decreased. Thus, the surface area of the bottom electrode cannot be effectively increased.
Furthermore, the formation of the photoresist layer is sometimes insufficient to cover completely the first oxide layer 112 in the peripheral area 104. As a result, while removing the first oxide layer 112 and the second oxide layer 118 in the cell array area 102, the first oxide layer 112 in the peripheral area 104 is undesirably removed. Thus, the foregoing problem caused by the height difference still exists. In addition, another conventional method solves the foregoing problem by reserving a guard region (not shown) in the peripheral area 104. However, the guard region increases the range of the peripheral area 104. This, in turn, causes the integration of a chip to decrease.